The first line of a power device datasheet is a marketing line, not an identifier. Wolfspeed's C4D40120D and C4D40120H carry the same title word for word — "4th Generation 1200 V, 40 A Silicon Carbide Schottky Diode" — and the same package marking, C4D40120. One is a single die, the other is two dies in one package, and the dual part states its surge withstand (i²t) per leg: 84.5 A²s against the single part's 305. Where a surge lands on one leg alone, that 3.6-fold gap is the real margin. Incoming inspection that compares the part marking against the purchase order passes both. The conclusion to act on before the detail starts: the document that governs a power device order is a part-specific specification you write, not the supplier's datasheet — and the reason is written into AEC-Q101 itself, where the supplier's datasheet ranks last of five in the document precedence order.
The problem: the ratings match and the parts do not
Below are the two Wolfspeed parts side by side, from the datasheet PDFs — C4D40120D at Rev. 9, September 2024, and C4D40120H at Rev. 4, August 2024. The dual part footnotes its table * Per Leg, ** Per Device.
| C4D40120D — dual die, TO-247-3 | C4D40120H — single die, TO-247-2 | |
|---|---|---|
| Datasheet title | 1200 V, 40 A SiC Schottky Diode | 1200 V, 40 A SiC Schottky Diode |
| Package marking | C4D40120 |
C4D40120 |
| IF @ TC = 25 °C | 56.5 / 113 A (per leg / per device) | 128 A |
| IFSM @ 25 °C, 10 ms | 130 A (per leg) | 247 A |
| i²t @ 25 °C, 10 ms | 84.5 A²s (per leg) | 305 A²s |
| i²t @ 110 °C | 60.5 A²s (per leg) | 300 A²s |
| VF typ / max, Tj 25 °C | 1.5 / 1.8 V at IF = 20 A | 1.5 / 1.8 V at IF = 40 A |
| RthJC typ | 0.29 (per device) / 0.57 (per leg) | 0.225 |
| Qc @ 800 V | 99 nC | 194.9 nC |
| Storage temperature | −55 to +135 °C (Tstg) | −55 to +150 °C (as case & storage temperature, Tc) |
Five practical traps come out of that table.
Forward voltage looks identical and is not comparable. Both datasheets read typ 1.5 V, max 1.8 V. The test currents are 20 A and 40 A. Any comparison spreadsheet that drops the test-condition column shows these two parts as equal on conduction loss. The dual part's datasheet nowhere guarantees its forward voltage when a single leg carries 40 A.
The surge withstand is quoted per leg, and the rule is not to convert that figure yourself in either direction but to require a device-level surge rating from the manufacturer. The reason is that i²t is an integral of current squared, so it does not scale the way a linear rating does. The two surge figures are not even independent of each other: i²t = IFSM²·tp/2 reproduces every printed value (130² × 0.005 = 84.5, 247² × 0.005 = 305, and Power Master's 135² × 0.005 = 91.1). Because it is a squared quantity, two legs sharing a surge evenly carry a device-level i²t of four times the per-leg figure, not twice — 4 × 84.5 = 338 A²s, slightly above the single die's 305, so under even sharing the dual is marginally the stronger part, not the weaker one a 3.6-fold headline implies. That 3.6-fold gap is real only in the opposite case: a fault or a topology that drives one leg alone leaves that leg with its bare 84.5 A²s. And even sharing is not guaranteed — the manufacturer does not warrant it, and below the forward-voltage crossover the negative temperature coefficient works against it — while the device-level rating itself is simply not printed. Between a figure you cannot safely convert and one that is not on the page, the number to hold in the specification is the manufacturer's.
Thermal resistance depends on which column you read. Per device, 0.29 against 0.225 looks close. A topology that loads only one leg — a single-phase boost stage, for instance — sees 0.57, which is 2.5 times the single-die part. The per-device figure assumes both legs are loaded evenly. Heatsink calculations carried over from one part to the other are wrong by that margin.
Storage limits differ, at 135 °C against 150 °C, and the two datasheets even attach them to different quantities. This is the kind of line nobody re-reads when a part number changes by one letter.
The package marking cannot resolve any of it. Both parts are laser-marked C4D40120. Distinguishing them at goods-in means counting leads or taking an X-ray.
None of this makes the dual arrangement inferior. Its total capacitive charge (QC) is 99 nC against 194.9 nC and its capacitance is roughly half, so switching loss goes the other way — which introduces its own re-verification problem, because a faster turn-on can invalidate the snubber and gate resistor values a design was tuned with. The defect is not the dual die. It is that a single die and a dual die are sold under one name.
Why the datasheet cannot carry the load
The per-leg convention is real, documented, and inconsistently visible
Power Master Semiconductor, a Korean IDM with a fab in Cheongju, published an application note on this exact reading problem — AN-CD2202, Rev. 1, 7 June 2022. It is the clearest manufacturer-side statement of the convention we found. The note spells out that the D in its PCW120D40D1 part number means dual die, that its single-die sibling PCA120S20D1 uses S for single and comes in a TO-247 2-lead package, and that its electrical characteristics table is headed "(Per Leg, TC = 25 °C unless otherwise noted)". Its thermal resistance is quoted both ways for the same reason as the Wolfspeed part — 0.69 °C/W per leg against 0.35 °C/W per device.
That header is the decisive evidence, and lead count is not. TO-247-3 single-die parts are ordinary: onsemi's NTHL080N120SC1 SiC MOSFET is a TO-247-3L single die with gate, drain and source on those three leads. Three leads mean "this could be dual," never "this is dual." What settles it is the per-leg/per-device notation and the terminal connection diagram on page one.
The same application note carries a second finding worth carrying into an evaluation. The forward-voltage temperature coefficient of that part crosses over at roughly 16 A — below it, forward voltage falls as temperature rises — and the note states explicitly that "this cross over point is different by device." The usual shorthand that SiC diodes are safe to parallel because of a positive temperature coefficient holds above the crossover and not below it, so light-load current sharing does not self-balance. Where the crossover sits is a question to ask a supplier; it is rarely printed.
We should be plain about the limits of this evidence. We verified the single-versus-dual naming problem at two manufacturers, Wolfspeed and Power Master Semiconductor. We did not audit the portfolios of Infineon, ROHM or STMicroelectronics for the same pattern, and we do not claim it is industry-wide. Two independent instances are enough to make it a checkpoint, not enough to make it a generalization. On our side we keep the two configurations as separate line items with thermal resistance quoted per leg on the dual — the split is visible on our SiC Schottky diode page.
An automotive grade buys documents, not performance
The second failure is a grade label read as a performance claim. We diffed the full text of two onsemi datasheets, line by line: NTHL080N120SC1 (industrial, Rev. 6, January 2023) and NVHL080N120SC1 (automotive, Rev. 4, May 2022).
Not one electrical or thermal number differs. VDSS 1200 V, ID 31 A at TC 25 °C, RDS(on) typ 80 / max 110 mΩ, RthJC 0.84 °C/W, QG(tot) 56 nC, EAS 171 mJ — identical throughout. The differences are the revision dates, brand wording in the title, the marking scheme, the application examples (UPS and DC-DC converter against automotive on-board charger and EV/HEV DC-DC), the package name spelling for the same physical CASE, and one feature bullet: AEC−Q101 Qualified and PPAP Capable.
That bullet is the product. What an automotive grade delivers here is qualification evidence, PPAP, change control and lot traceability — not a better die. Buying it for performance means paying for documents you then do not ask to see.
AEC-Q101 is a self-declaration, and it says so
The standard is blunt about its own status. AEC-Q101 Rev E, dated 1 March 2021, states at §1.3.1 that "there are no 'certifications' for AEC-Q101 qualification and there is no certification board run by AEC to qualify parts." There is no certificate to collect, because there is no body that issues one. The supplier runs the tests and declares the result; the evidence is the qualification test report together with the Certificate of Design, Construction and Qualification described in §3.1 and Appendix 2.
Four provisions in the same document decide what a buyer actually receives.
The datasheet ranks last. §2.1 sets document precedence as (a) the purchase order, (b) the individual agreed-upon part specification, (c) AEC-Q101 itself, (d) the reference documents, and (e) the supplier's datasheet. If no agreed part specification exists at (b), the only technical document in the dispute is the one ranked fifth — the one the supplier wrote alone and revises alone.
"Tested to" is not "qualified." §1.3.1 permits a supplier, in agreement with the user, to qualify at sample sizes and conditions less stringent than the standard requires — but that part cannot be called AEC-Q101 qualified until the unfulfilled requirements are completed. A quotation saying "tested per AEC-Q101" is not making the same claim as "AEC-Q101 qualified," and the difference is invisible unless you ask which requirements were reduced.
The data may not be from your part. §2.2 allows generic family data: qualify the family's "four corners" and the parts in between are covered. Only ESD HBM/CDM and parametric verification are mandated as part-specific under §4.2. The standard then hands the decision to the buyer — "The user(s) will be the final authority on the acceptance of generic data in lieu of specific part test data." That is a decision to make, not a courtesy to request.
Change notification is whatever the contract says. §3.2.1 reads, in full: "The supplier will meet mutually agreed upon requirements for product/process changes." No notice period, no channel, no format. An AEC-Q101 part carries no automatic PCN window. (JEDEC's JESD46 was superseded by the joint JEDEC/ECIA/IPC standard J-STD-046 in July 2016, and public summaries describe a 90-day pre-shipment notification requirement in it. We could not obtain the standard text — it is paid — so we state that as a secondary account rather than a verified provision, and we could not confirm whether it regulates last-time-buy windows at all.)
For scale, the qualification behind the label runs a minimum of three lots × 77 pieces per lot (§2.3.4), over an operational range of at least −40 °C to +125 °C (§1.3.1), with HTRB and HTGB at 1000 hours, H3TRB at 1000 hours under 85 °C/85% RH, temperature cycling at 1000 cycles, and HAST at 96 hours at 130 °C/85% RH. Several of those have documented reductions — temperature cycling drops to 400 cycles if run at Tj+25 °C or 175 °C, HTGB to 500 hours at Tj+25 °C — which is a further reason the report matters more than the label.
One clause is little known and applies directly to SiC Schottky diodes. A lettered note to Table 2 (Note X) allows that for switching parts that can experience thermal runaway in HTRB under a DC reverse condition, the maximum rated junction temperature at rated DC reverse voltage may not be specified, and requires the conditions actually used to be stated in the qualification test plan or report. In other words, the 1000-hour HTRB behind a SiC diode's qualification may not have been run at the part's rated junction temperature, and the standard permits that. The question to put to a supplier is not "did it pass HTRB" but "at what voltage and what junction temperature."
The 25 °C column hides the differences that matter
Devices are compared at 25 °C and operated near their limit. The multipliers between those two states are not a property of the technology; they differ part to part, from the same primary datasheets.
| Parameter | Part | 25 °C | At temperature | Multiplier |
|---|---|---|---|---|
| VF (max) | C4D40120D / C4D40120H | 1.8 V | 3.0 V @ 175 °C | ×1.67 |
| IR (max) | C4D40120D | 200 µA | 400 µA @ 175 °C | ×2 |
| IR (max) | C4D40120H | 300 µA | 500 µA @ 175 °C | ×1.67 |
| IR (max) | PCW120D40D1 | 100 µA | 300 µA @ 175 °C | ×3 |
| IDSS (max) | NTHL/NVHL080N120SC1 | 100 µA | 1 mA @ 175 °C | ×10 |
| RDS(on) (typ) | NTHL/NVHL080N120SC1 | 80 mΩ | 114 mΩ @ 150 °C | ×1.43 |
The high-temperature column mixes test-condition bases: Power Master's leakage is at TC = 175 °C, the Wolfspeed and onsemi figures at Tj = 175 °C. Each part's own multiplier stands regardless, but by this article's own rule — align the conditions before placing numbers next to each other — the mixing is worth stating in the table that makes the point.
Reverse leakage multipliers spread from ×1.67 to ×10 across these four parts. A standby-loss calculation built on the 25 °C column can be out by an order of magnitude, and the ranking of two candidate parts at 25 °C can invert at operating temperature.
Two secondary observations sit inside the same table. First, whether high-temperature values appear at all is itself a signal — all four parts here publish them, and a datasheet that stops at 25 °C either did not measure or chose not to print. Second, where they do appear they are often typical rather than maximum: the 175 °C forward voltage of PCW120D40D1 gives typ 1.8 V with the max cell empty, and onsemi's 150 °C on-resistance gives typ 114 mΩ with no max. A typical value is not a guarantee, and worst-case thermal design needs the guarantee. Test conditions have to be aligned before any of these numbers are placed next to each other — onsemi specifies on-resistance at VGS = 20 V and ID = 20 A, and SiC MOSFET on-resistance is sensitive enough to gate voltage that a competing part quoted at 15 V or 18 V is not comparable at all. That is the same trap as the 20 A / 40 A forward voltage, one level up; it is why we settle the gate-drive family before quoting anything on the SiC MOSFET line.
Who made the die changes what a supplier can tell you
Chinese SiC suppliers divide into two structures: large vertically integrated power semiconductor makers running their own fabs, and fabless designers who place wafers with SiC foundries — some domestic, some in Taiwan or Europe. The distinction is not about quality. It is about what information exists to give you.
An in-house fab links the wafer lot to the assembly lot inside one company, analyses a die-attributable failure itself, manages only its own process changes, and decides its own requalification. A foundry-based supplier does none of those wholly on its own: the wafer lot record belongs to the foundry and parts of it cannot be handed over, a die-attributable 8D goes back to the foundry and returns slower and abridged, a foundry process change reaches the supplier through one extra link and therefore late, and a foundry change amounts in practice to a new qualification. That reasoning follows from the requalification provisions of AEC-Q101 §3.2 and from how the two structures work; we have not verified it against any specific supplier's actual conduct, so treat it as the reason to ask a question rather than as a finding. The question is two-part: do you own the fab, and if not, does your foundry agreement oblige the foundry to notify you of process changes, and does your contract pass that notification through to you? The second half is where the exposure sits, and it is rarely asked.
Korea is acquiring a domestic option here, slowly. DB HiTek announced on 9 September 2026 that it had completed reliability qualification of a 200 mm 1200 V SiC MOSFET process, describing it as the first completed 1200 V eight-inch SiC foundry flow; its second-generation process is stated at 2.5 mΩ·cm² or below with threshold voltage above 3 V at an 18 V gate, and a third generation targeting 2.3 mΩ·cm² and short-circuit withstand above 2.5 µs is due to be disclosed in November 2026. The schedule is the part that matters for anyone buying now: general customer access is stated for Q2 2027 with mass production targeted in 2027, and the announcement makes no mention of AEC-Q101 or automotive qualification. For an order that has to be placed this quarter, it is not an alternative. Substrate supply underneath all of this is its own moving problem, covered in our note on the six- to eight-inch SiC wafer transition.